Secure management of the Intellectual Property in the Cloud
Keywords:cloud computing, security, System-on-Chip, FPGA, partial reconfiguration, scalability, Network-on-Chip
AbstractThe development of distributed computing systems – and especially cloud computing – has raised new vulnerability challenges regarding intellectual property (IP) generated by moving client’s data to the cloud infrastructure. Sensitive data is thus located at a remote facility, where clients are not granted full control and administrative access, generating critical concerns about the security of their intellectual property. This paper proposes an approach based on securing the IP in the cloud using reconfigurable hardware architectures – FPGA (Field Programmable Gate Array)-based System-on-Chip (SoC): IP elements being integrated in the programmable logic as IP cores, benefiting from the security and management of on-chip integrated IP modules. Also, by transcending the cloud computing model from macro- to micro-structures, integrated IP cores gain a higher degree of adaptability and can be easily interconnected using Network-on-Chip architectures.
Sabahi, Farzad. "Cloud computing security threats and responses." Communication Software and Networks (ICCSN), 2011 IEEE 3rd International Conference on. IEEE, 2011.
Grot, Boris, and Stephen W. Keckler. "Scalable on-chip interconnect topologies." In 2nd Workshop on Chip Multiprocessor Memory Systems and Interconnects. 2008.
Glas, Benjamin, et al. "A system architecture for reconfigurable trusted platforms." Proceedings of the conference on Design, automation and test in Europe. ACM, 2008.
Lu, Hang, Guihai Yan, Yinhe Han, Binzhang Fu, and Xiaowei Li. "RISO: relaxed network-on-chip isolation for cloud processors." In Proceedings of the 50th Annual Design Automation Conference, p. 38. ACM, 2013.
Kang, Peter. Intellectual Property and Legal Issues Surrounding Cloud Computing. Strafford Publishing, 2011
Cloud Computing: Intellectual Property Legal Issues - Protecting IP Rights and Mitigating Infringement Risks in Virtual Storage and Applications. Strafford Publishing Webinar, 2011
Intel Single-chip Cloud Computer (2013), http://www.intel.com
Nychis, George, Chris Fallin, Thomas Moscibroda, and Onur Mutlu. "Next generation on-chip networks: What kind of congestion control do we need?." In Proceedings of the 9th ACM SIGCOMM Workshop on Hot Topics in Networks, p. 12. ACM, 2010.
Dally, William J., and Brian Towles. "Route packets, not wires: On-chip interconnection networks." In Design Automation Conference, 2001. Proceedings, pp. 684-689. IEEE, 2001.
Bjerregaard, Tobias, and Shankar Mahadevan. "A survey of research and practices of network-on-chip." ACM Computing Surveys (CSUR) 38.1 (2006): 1.
Moller, L., Grehs, I., Calazans, N., & Moraes, F. (2006, August). Reconfigurable systems enabled by a Network-on-Chip. In Field Programmable Logic and Applications, 2006. FPL'06. International Conference on (pp. 1-4). IEEE, 2012.
Schramm, Martin, and Andreas Grzemba. "Reconfigurable trust for embedded computing platforms." Applied Electronics (AE), 2012 International Conference on. IEEE, 2012.
McNeil, Steven. "Solving Today's Design Security Concerns." Xilinx Corporation, 2010.
Peterson, Ed. “Developing Tamper Resistant Designs with Xilinx Virtex-6 and 7 Series FPGAs” Application Note. Xilinx Corporation, 2013.
Xilinx Backgrounder Paper “A Generation Ahead for Smarter Systems: 9 Reasons why the Xilinx Zynq-7000 All Programmable
SoC Platform is the Smartest Solution” Xilinx Corporation, 2013.
Eguro, Ken, and Ramarathnam Venkatesan. "FPGAs for trusted cloud computing." Field Programmable Logic and Applications (FPL), 2012 22nd International Conference on. IEEE, 2012.
Blodget, Brandon, Christophe Bobda, Michael Hübner, and Adronis Niyonkuru. "Partial and dynamically reconfiguration of Xilinx Virtex-II FPGAs." In Field Programmable Logic and Application, pp. 801-810. Springer Berlin Heidelberg, 2004.
Takai, Teresa M. “Cloud Computing Strategy”. Department of Defense, Washington DC, Chief Information Officer, 2012.
How to Cite
Authors who publish with this journal agree to the following terms:
- Authors retain copyright and grant the journal right of first publication with the work simultaneously licensed under a Creative Commons Attribution License that allows others to share the work with an acknowledgement of the work's authorship and initial publication in this journal.
- Authors are able to enter into separate, additional contractual arrangements for the non-exclusive distribution of the journal's published version of the work (e.g., post it to an institutional repository or publish it in a book), with an acknowledgement of its initial publication in this journal.
- Authors are permitted and encouraged to post their work online (e.g., in institutional repositories or on their website) prior to and during the submission process, as it can lead to productive exchanges, as well as earlier and greater citation of published work (See The Effect of Open Access).
- The author(s) is responsible for the correctness and legality of the paper content.
- Papers that are copyrighted or published will not be taken into consideration for publication in JMEDS It is the author(s) responsibility to ensure that the paper does not cause any copyright infringements and other problems.
- It is the responsibility of the author(s) to obtain all necessary copyright release permissions for the use of any copyrighted materials in the paper prior to the submission.
- The Author(s) retains the right to reuse any portion of the paper, in future works, including books, lectures and presentations in all media, with the condition that the publication by JMEDS is properly credited and referenced.
JMEDS articles by Journal of Mobile, Embedded and Distributed Systems (JMEDS) is licensed under a Creative Commons Attribution 4.0 International License.
Based on a work at http://jmeds.eu.
Permissions beyond the scope of this license may be available at http://jmeds.eu/index.php/jmeds/about/submissions#copyrightNotice.